WCDMA RF System introduction
1. Transmitter
The W-CDMA Transmitter ASIC is a low voltage transmitter intended for use within W-CDMA handheld mobile terminals.
Delivering output power in 0.25 dB steps, and converting the I and Q output signals generated from within the
baseband controller from baseband to RF, this microcircuit comprises the following internal blocks:
1.1 Reconstruction filter
1.2 IQ modulator
1.3 Variable Gain Amplifier (VGA)
1.4 Intermediate Frequency Band Pass filter (IF BP)
1.5 RF mixer and buffer
1.6 IF PLL
1.1 Reconstruction filter
The reconstruction filters consist of input buffers that provide the correct DC biasing for the preceding
DAC in the Ericsson DB 2100, and a low-pass filter for removing the unwanted high frequency
components from the baseband input waveform.
The filter inputs are adapted for use with a current-source type of input signal.
The bandwidth and Q factor of these filters are programmable via the serial bus words LPBW and LPQ,
respectively. The logical signals RECDCI and RECDCQ compensate DC offsets between the I and Q channels
to reduce IF LO leakage.
The most significant bits of the RECDCI and RECDCQ signals are the significant sign bits for controlling this compensation.
The two following bits are responsible for controlling the applied level of signal magnitude.
1.2 IQ modulator
The IQ modulator receives the incoming I and Q analog baseband signals at baseband frequency and convert
them to an intermediate frequency of 380 MHz. The logical signal IQGAIN is used to switch the gain of the block.
The block accepts a 760 MHz LO signal and generates the needed I and Q phases at 380 MHz.
1.3
Variable gain amplifier Comprising two cascaded variable gain amplifiers, the VGA, together with the RF mixer, controls the power
of the transmitter. The first of these two amplifiers, the so-called QVGA, enables fine-tuning of the
transmitter by varying the gain in 0.25 dB steps, that is, 0/0.25/0.5/0.75 dB. The second amplifier provides
a 54 dB gain range in 1 dB steps (54 steps = 55 levels).
For the purpose of the 54 dB VGA, the 6-bit logical signal VGAGAIN is used. For the control of the QVGA,
the 2-bit logical signal QVGAGAIN is used. The VGA and QVGA together minimize the maximum gain gap
defined in Figure 3.9 below.
1.4 IF band pass filter
The IF filter suppresses up-converted noise out of band and unwanted frequency components generated in the IQ
modulator and subsequently amplified in the VGA.
The filter is tunable by an external tuned RLC load as shown in Figure 3.10.
1.5 RF mixer and buffer
The RF mixer converts the signal output from the IF BP filter from an intermediate frequency (IF)
to the final radio frequency (RF). The mixer can be switched between three different gain levels:
high gain (HG), medium gain (MG), and low gain (LG). The LO buffer provides the buffering for either an
internal LO signal generated within the internal RFPLL, or an external LO signal applied to the RFLO/RFLOBAR pins.
External DC blocking is necessary for the external LO signal. The logical signal LOINTEXT is used for the choice
of internal or external LO.
The RF buffer is used to drive an external PA stage. The buffer is of an open-collector design.
The gain switching together with the VGA amplifier at IF enable an output power control in 0.25 dB steps
over no less than 80 dB. To minimize power consumption, the bias current for the RF buffer is programmable
from the serial bus
1.6 IF PLL
The IF LO frequency synthesis comprises the following four parts:
※ Input buffer: 13 MHz input buffer with DC-biasing provided at source.
※ VCO: Operating on 1.52 GHz, which is four times the TX-IF frequency (380 MHz) and eight times the RX-IF (190 MHz),
this is a fully integrated balanced LC oscillator with on-chip resonator. On-chip varactors are used
to tune the VCO frequency.
※ Prescaler
※ Phase detector with charge pump: For maintaining, check on the VCO center frequency,
the tuning voltage is set to Vcc/2 via the serial bus bit TBIFVCO.
External DC blocking capacitors have to be used on the IFLO/IFLOBAR signals
